The present invention relates to an analog to digital convertor, and in particular, can be preferably used for an analog to digital convertor accompanied by calibration.
In an analog to digital convertor (ADC), linearity caused by mismatch of elements in the ADC and a conversion error due to offset have been generally corrected using a digital calibration technique. Here, the “analog to digital convertor” is referred to an analog to digital conversion circuit, an AD convertor, an AD conversion circuit, or an ADC in some cases. Further, “AD” is written as “A/D” in some cases. Further, the “mismatch of elements” includes mismatch with respect to a design value, namely, a relative error and relative variation generated when the elements are designed to be supposed to have the same elemental value or elemental values with a specified ratio, in addition to manufacturing variation and an absolute error. In order to remove an error of a correction value generated due to noise such as elemental noise in calibration, correction values are obtained by a plurality of operations, and the final correction value is obtained by averaging the operation results of the correction values. Alternatively, the final correction value is similarly obtained in general by an operation by which the same effect can be obtained, for example, by allowing the operation results to pass through a low-pass filter or by accumulating the operation results.
Japanese Unexamined Patent Application Publication No. 2004-222274 discloses a circuit technique of correcting an error of an output voltage of a digital to analog convertor and a gain error of an amplifying circuit in a pipeline stage of a pipeline-type ADC. FIG. 2 of the literature shows an error correction data generation circuit, a DAC error correction circuit, and a gain error correction circuit, and an effect of noise can be reduced by arranging an averaging circuit on the input side or the output side of the error correction data generation circuit. It should be noted that the “digital to analog convertor” is referred to as a digital to analog conversion circuit, a DA convertor, a DA conversion circuit, or a DAC in some cases. Further, “DA” is written as “D/A” in some cases.
“S. Y. Chuang and T. L. Sculley, “A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A to D converter”, Journal of Solid-State Circuit, vol. 37, No. 6, June 2002” discloses a pipeline-type ADC in which an error correction circuit is provided in each stage (see FIG. 1 of the literature), and a calibration circuit coupled to the output of the ADC shown in FIG. 6 of the literature includes an averaging circuit (2048 averaging and ALU circuit).
A calibration method in which an element parameter in an analog circuit is finely adjusted by feeding back an operation result in a digital region to an analog region has been generally used. For example, there is a self-trimming circuit shown in FIG. 3 of “S. T. Ryu, “A 14b-Linear Capacitor Self-Trimming Pipelined ADC”, Journal of Solid-State Circuit, vol. 39, No. 11, November 2004”.